`include "chunjun_define.sv" 
`include "chunjun_lib_define.sv" 
`define CHUNJUN_CORE_N 1

module chunjun_dcu_tb();

// 时钟和复位信号
logic clk;
logic rst_n;

logic [`CHUNJUN_CORE_N-1:0][4-1:0]                                   dcu_ram_tag_cs   ;
logic [`CHUNJUN_CORE_N-1:0][4-1:0]                                   dcu_ram_tag_wr   ;
logic [`CHUNJUN_CORE_N-1:0][4-1:0][`CHUNJUN_DC_SETIDX_W-1:0]         dcu_ram_tag_addr ;
logic [`CHUNJUN_CORE_N-1:0][4-1:0][`CHUNJUN_DC_TAG_RAM_DATA_W-1:0]   dcu_ram_tag_wen  ;
logic [`CHUNJUN_CORE_N-1:0][4-1:0][`CHUNJUN_DC_TAG_RAM_DATA_W-1:0]   dcu_ram_tag_wdata;
logic [`CHUNJUN_CORE_N-1:0][4-1:0][`CHUNJUN_DC_TAG_RAM_DATA_W-1:0]   dcu_ram_tag_rdata;

logic [`CHUNJUN_CORE_N-1:0][4-1:0]                                   dcu_ram_data0_cs   ;
logic [`CHUNJUN_CORE_N-1:0][4-1:0]                                   dcu_ram_data0_wr   ;
logic [`CHUNJUN_CORE_N-1:0][4-1:0][`CHUNJUN_DC_DATA_RAM_ADDR_W-1:0]  dcu_ram_data0_addr ;
logic [`CHUNJUN_CORE_N-1:0][4-1:0][`CHUNJUN_DC_DATA_RAM_DATA_W-1:0]  dcu_ram_data0_wen  ;
logic [`CHUNJUN_CORE_N-1:0][4-1:0][`CHUNJUN_DC_DATA_RAM_DATA_W-1:0]  dcu_ram_data0_wdata;
logic [`CHUNJUN_CORE_N-1:0][4-1:0][`CHUNJUN_DC_DATA_RAM_DATA_W-1:0]  dcu_ram_data0_rdata;

logic [`CHUNJUN_CORE_N-1:0][4-1:0]                                   dcu_ram_data1_cs   ;
logic [`CHUNJUN_CORE_N-1:0][4-1:0]                                   dcu_ram_data1_wr   ;
logic [`CHUNJUN_CORE_N-1:0][4-1:0][`CHUNJUN_DC_DATA_RAM_ADDR_W-1:0]  dcu_ram_data1_addr ;
logic [`CHUNJUN_CORE_N-1:0][4-1:0][`CHUNJUN_DC_DATA_RAM_DATA_W-1:0]  dcu_ram_data1_wen  ;
logic [`CHUNJUN_CORE_N-1:0][4-1:0][`CHUNJUN_DC_DATA_RAM_DATA_W-1:0]  dcu_ram_data1_wdata;
logic [`CHUNJUN_CORE_N-1:0][4-1:0][`CHUNJUN_DC_DATA_RAM_DATA_W-1:0]  dcu_ram_data1_rdata;

logic [1:0]         lsu_dcu_ld_req_valid_m1;
logic [1:0] [31:0]  lsu_dcu_ld_req_addr_m1;
logic [1:0] [1:0]   lsu_dcu_ld_req_size_m1;
logic [1:0] [3:0]   lsu_dcu_ld_req_lsqid_m1;

//bus interface
logic                                                           bmu_dcu_r_vld; //BMU向dcu发送读数据的valid指示信号
logic                                                           dcu_bmu_r_rdy; //dcu向BMU返回读数据的ready指示信号，支持反压
logic [4-1:0]                                                   bmu_dcu_r_id; //BBMU向dcu返回读传输ID信号，用于支持乱序传输
logic [`CHUNJUN_MBUS_DATA_W-1:0]                                bmu_dcu_r_data; //BMU向dcu发送读数据
logic [1:0]                                                     bmu_dcu_r_resp; //BMU告诉DCU读数据请求的响应，00:OKAY; 01:EXOKAY; 10:SLVERR; 11:DECERR
logic                                                           bmu_dcu_r_last; //BMU告诉DCU读数据请求是否是最后一个数据，1:是最后一个数据; 0:不是最后一个数据

// SBU tag_req
logic                                                     sbu_dcu_tag_req_vld_m1; //SBU向Dcache发送写请求valid指示信号
logic                                                     dcu_sbu_tag_req_rdy_m1; //Dcache接收SBU发出写请求ready指示信号
logic [32-1:0]                                            sbu_dcu_tag_req_addr_m1; //SBU向Dcache发送写请求的地址信息当前版本SBU按照size对齐的方式发送地址给dcache，通过wstrb区分有效写数据
logic [$clog2(6)-1:0]                                     sbu_dcu_tag_req_sbqid_m1; //SBU向dcache发出写请求的ID信息
logic                                                     sbu_dcu_tag_req_excl_m1; //sbu向dcu发出写请求的排他属性1'b0：非exclusive写请求1'b1：exclusive写请求*说明：目前nouse
logic                                                     sbu_dcu_tag_req_idempotency_m1; //0: Non-idempotency (device); 1: idempotency (non-device)
logic [2:0]                                               sbu_dcu_tag_req_inner_ma_m1; //SBU发送给DCU的store请求的inner memory attributebit[2] - 1'b0: No-Write-Allocate; 1'b1: Write-Allocatebit[1] - 1'b0: No-Read-Allocate; 1'b1: Read-Allocate，SBU只发出写请求，DCU可忽略此bitbit[0] - 1'b0: Non-Cacheable; 1'b1: Cacheable，这里tie1，固定为cachebale
logic [2:0]                                               sbu_dcu_tag_req_outer_ma_m1; //SBU发送给DCU的store请求的outer memory attributebit[2] - 1'b0: No-Write-Allocate; 1'b1: Write-Allocatebit[1] - 1'b0: No-Read-Allocate; 1'b1: Read-Allocate，SBU只发出写请求，DCU可忽略此bitbit[0] - 1'b0: Non-Cacheable; 1'b1: Cacheable
logic                                                     sbu_dcu_tag_req_priv_m1; //1: priviledged  0:unpriviledged
logic                                                     sbu_dcu_tag_req_master_m1; //指示当前请求来源，0:来自于内核1:来自于调试器

// Cache Maintenance Operation (CMO)
// 3'b0000: Non-CMO
// 3'b0001: CBO.INVAL (Invalidate)
// 3'b0010: CBO.CLEAN
// 3'b0011: CBO.FLUSH
// 3'b101: invalidate all dcache
// 3'b110: clean all dcache
// 3'b111: flush all dcache
logic [2:0]                                               sbu_dcu_tag_req_cmoop_m1; //3'b000：非CMO请求,3'b001：CBO.INVAL,3'b010：CBO.CLEAN,3'b011：CBO.FLUSH,3'b101：Invalidate all dcache,3'b110：Clean all dcache,3'b111：Flush all dcache



chunjun_mem_wrap_top u_chunjun_mem_wrap_top(
    .clk                                (clk),
    .rst_n                              (rst_n),
    .dcu_ram_tag_cs                     (dcu_ram_tag_cs                     ),
    .dcu_ram_tag_wr                     (dcu_ram_tag_wr                     ),
    .dcu_ram_tag_addr                   (dcu_ram_tag_addr                   ),
    .dcu_ram_tag_wen                    (dcu_ram_tag_wen                    ),
    .dcu_ram_tag_wdata                  (dcu_ram_tag_wdata                  ),
    .dcu_ram_tag_rdata                  (dcu_ram_tag_rdata                  ),

    .dcu_ram_data0_cs                   (dcu_ram_data0_cs                   ),
    .dcu_ram_data0_wr                   (dcu_ram_data0_wr                   ),
    .dcu_ram_data0_addr                 (dcu_ram_data0_addr                 ),
    .dcu_ram_data0_wen                  (dcu_ram_data0_wen                  ),
    .dcu_ram_data0_wdata                (dcu_ram_data0_wdata                ),
    .dcu_ram_data0_rdata                (dcu_ram_data0_rdata                ),

    .dcu_ram_data1_cs                   (dcu_ram_data1_cs                   ),
    .dcu_ram_data1_wr                   (dcu_ram_data1_wr                   ),
    .dcu_ram_data1_addr                 (dcu_ram_data1_addr                 ),
    .dcu_ram_data1_wen                  (dcu_ram_data1_wen                  ),
    .dcu_ram_data1_wdata                (dcu_ram_data1_wdata                ),
    .dcu_ram_data1_rdata                (dcu_ram_data1_rdata                )

);

// 实例化被测试模块
chunjun_dcu u_chunjun_dcu (
    .core_priv_mode(2'b00),
    .dcu_init_busy(),
    .dcu_idle(),
    
    // CSR接口
    .pcu_csr_msyscfg(32'h00000003),  // DCache和ECC使能
    .pcu_csr_mauxcfg(32'h0),
    .pcu_csr_meictl(32'h0),
    .pcu_csr_meibmap(32'h0),
    .pcu_csr_meibmaph(32'h0),
    
    // LSU接口 - Load请求
    .lsu_dcu_ld_req_valid_m1(lsu_dcu_ld_req_valid_m1), //2bit
    .dcu_lsu_ld_req_ready_m1(),
    .lsu_dcu_ld_req_addr_m1(lsu_dcu_ld_req_addr_m1), //32bit = 04
    .lsu_dcu_ld_req_size_m1(lsu_dcu_ld_req_size_m1),  //4'b1111
    .lsu_dcu_ld_req_lsqid_m1(lsu_dcu_ld_req_lsqid_m1),//12'd1
    .lsu_dcu_ld_req_idempotency_m1(2'b11), // 0: Non-idempotency (device); 1: idempotency (non-device)
// bit[2] - 0: non-write-allocate; 1: write-allocate
// bit[1] - 0: non-read-allocate; 1: read-allocate  
// bit[0] - 0: non-cacheable; 1: cacheable
    .lsu_dcu_ld_req_inner_ma_m1(6'h3f),
    .lsu_dcu_ld_req_outer_ma_m1(6'h3f),
    .lsu_dcu_ld_req_excl_m1(2'b00), //发送给DCU的读请求是否为排他读0：非exclusive load,1：exclusive load
    .lsu_dcu_ld_req_master_m1(2'b00),
    .lsu_dcu_ld_req_samecl_m1(1'b0),
    
    // LSU接口 - M2阶段
    .lsu_dcu_ld_req_ma_update_m2(2'b00),
    .lsu_dcu_ld_req_idempotency_m2(2'b00),
    .lsu_dcu_ld_req_inner_ma_m2(6'h0),
    .lsu_dcu_ld_req_outer_ma_m2(6'h0),
    .lsu_dcu_ld_req_cancel_m2(2'b00),
    
    // LSU接口 - Load响应
    .dcu_lsu_ld_replay_cause_m2(),
    .dcu_lsu_ld_replay_lsqid_m2(),
    .dcu_lsu_ld_replay_mbid_m2(),
    .dcu_lsu_mb_rls_array(),
    .dcu_lsu_ld_rsp_valid_m2(),
    .lsu_dcu_ld_rsp_ready_m2(2'b11),
    .dcu_lsu_ld_rsp_data_m2(),
    .dcu_lsu_ld_rsp_lsqid_m2(),
    .dcu_lsu_ld_rsp_buserr_m2(),
    .dcu_lsu_ld_rsp_excl_okay_m2(),
    .dcu_lsu_ld_rsp_valid_m3(),
    .dcu_lsu_ld_rsp_raserr_m3(),
    .dcu_lsu_ld_rsp_replay_m3(),
    .dcu_lsu_ld_rsp_lsqid_m3(),
    
    // LSU接口 - Flush和Prefetch
    .lsu_dcu_flush_valid(1'b0),
    .lsu_dcu_flush_lsqid(7'h0),
    .lsu_dcu_prefetch_valid(1'b0),
    .lsu_dcu_prefetch_write(1'b0),
    .lsu_dcu_prefetch_addr(32'h0),
    .lsu_dcu_prefetch_outer_ma(3'h0),
    
    // SBU接口 - Tag请求
    .sbu_dcu_tag_req_vld_m1(sbu_dcu_tag_req_vld_m1),
    .dcu_sbu_tag_req_rdy_m1(dcu_sbu_tag_req_rdy_m1),
    .sbu_dcu_tag_req_addr_m1(sbu_dcu_tag_req_addr_m1),
    .sbu_dcu_tag_req_sbqid_m1(sbu_dcu_tag_req_sbqid_m1),
    .sbu_dcu_tag_req_excl_m1(sbu_dcu_tag_req_excl_m1),
    .sbu_dcu_tag_req_idempotency_m1(1'b1), //no_dvice
    .sbu_dcu_tag_req_inner_ma_m1(sbu_dcu_tag_req_inner_ma_m1),
    .sbu_dcu_tag_req_outer_ma_m1(sbu_dcu_tag_req_outer_ma_m1),
    .sbu_dcu_tag_req_priv_m1(sbu_dcu_tag_req_priv_m1),
    .sbu_dcu_tag_req_master_m1(sbu_dcu_tag_req_master_m1),
    .sbu_dcu_tag_req_cmoop_m1(sbu_dcu_tag_req_cmoop_m1),
    
    // SBU接口 - Tag响应
    .dcu_sbu_tag_rsp_vld_m2(),
    .dcu_sbu_tag_rsp_hit_m2(),
    .dcu_sbu_tag_rsp_status_m2(),
    .dcu_sbu_tag_rsp_way_m2(),
    .dcu_sbu_tag_rsp_sbqid_m2(),
    .dcu_sbu_tag_rsp_excl_ok_m2(),
    .dcu_sbu_tag_rsp_raserr_m2(),
    .dcu_sbu_tag_replay_cause_m2(),
    .dcu_sbu_tag_replay_mbid_m2(),
    .dcu_sbu_cmo_done(),
    
    // SBU接口 - Fill Done
    .dcu_sbu_filldone(),
    .dcu_sbu_filldone_err(),
    .dcu_sbu_filldone_sbqid(),
    .dcu_sbu_mb_rls_array(),
    .dcu_sbu_eb_done_array(),
    
    // SBU接口 - Data请求
    .sbu_dcu_data_req_vld_m1(1'b0),
    .dcu_sbu_data_req_rdy_m1(),
    .sbu_dcu_data_req_type_m1(1'b0),
    .sbu_dcu_data_req_status_m1(1'b0),
    .sbu_dcu_data_req_way_m1(2'h0),
    .sbu_dcu_data_req_addr_m1(32'h0),
    .sbu_dcu_data_req_mask_m1(2'h0),
    .sbu_dcu_data_req_excl_m1(1'b0),
    .sbu_dcu_data_req_wdata_m1(64'h0),
    .sbu_dcu_data_req_ecc_m1(14'h0),
    .sbu_dcu_data_req_wstrb_m1(8'h0),
    .sbu_dcu_data_req_sbqid_m1(3'h0),
    .sbu_dcu_data_req_zero_m1(1'b0),
    
    // SBU接口 - Data响应
    .dcu_sbu_data_rsp_vld_m3(),
    .dcu_sbu_data_rsp_rdata_m3(),
    .dcu_sbu_data_rsp_raserr_m3(),
    .dcu_sbu_data_rsp_sbqid_m3(),
    
    // Waylock接口
    .sbu_dcu_waylock_vld(6'h0),
    .sbu_dcu_waylock_way(24'h0),
    .sbu_dcu_waylock_index(30'h0),
    
    // AXI接口 - 读地址通道
    .dcu_bmu_ar_vld(),
    .bmu_dcu_ar_rdy(1'b1),
    .dcu_bmu_ar_id(),
    .dcu_bmu_ar_addr(),
    .dcu_bmu_ar_size(),
    .dcu_bmu_ar_len(),
    .dcu_bmu_ar_burst(),
    .dcu_bmu_ar_lock(),
    .dcu_bmu_ar_cache(),
    .dcu_bmu_ar_prot(),
    .dcu_bmu_ar_master(),
    
    // AXI接口 - 读数据通道
    .bmu_dcu_r_vld(bmu_dcu_r_vld),
    .dcu_bmu_r_rdy(dcu_bmu_r_rdy),
    .bmu_dcu_r_id(bmu_dcu_r_id),
    .bmu_dcu_r_data(bmu_dcu_r_data),
    .bmu_dcu_r_resp(bmu_dcu_r_resp),
    .bmu_dcu_r_last(bmu_dcu_r_last),
    
    // AXI接口 - 写地址通道
    .dcu_bmu_aw_vld(),
    .bmu_dcu_aw_rdy(1'b1),
    .dcu_bmu_aw_id(),
    .dcu_bmu_aw_addr(),
    .dcu_bmu_aw_size(),
    .dcu_bmu_aw_len(),
    .dcu_bmu_aw_burst(),
    .dcu_bmu_aw_lock(),
    .dcu_bmu_aw_cache(),
    .dcu_bmu_aw_prot(),
    .dcu_bmu_aw_master(),
    .dcu_bmu_aw_atop(),
    
    // AXI接口 - 写数据通道
    .dcu_bmu_w_vld(),
    .bmu_dcu_w_rdy(1'b1),
    .dcu_bmu_w_data(),
    .dcu_bmu_w_strb(),
    .dcu_bmu_w_last(),
    
    // AXI接口 - 写响应通道
    .bmu_dcu_b_vld(1'b0),
    .dcu_bmu_b_rdy(),
    .bmu_dcu_b_id(4'h0),
    .bmu_dcu_b_resp(2'h0),
    
    // RAM接口
    .dcu_ram_tag_cs(dcu_ram_tag_cs),
    .dcu_ram_tag_wr(dcu_ram_tag_wr),
    .dcu_ram_tag_addr(dcu_ram_tag_addr),
    .dcu_ram_tag_wen(dcu_ram_tag_wen),
    .dcu_ram_tag_wdata(dcu_ram_tag_wdata),
    .dcu_ram_tag_rdata(dcu_ram_tag_rdata),
    
    .dcu_ram_data0_cs(dcu_ram_data0_cs),
    .dcu_ram_data0_wr(dcu_ram_data0_wr),
    .dcu_ram_data0_addr(dcu_ram_data0_addr),
    .dcu_ram_data0_wen(dcu_ram_data0_wen),
    .dcu_ram_data0_wdata(dcu_ram_data0_wdata),
    .dcu_ram_data0_rdata(dcu_ram_data0_rdata),
    
    .dcu_ram_data1_cs(dcu_ram_data1_cs),
    .dcu_ram_data1_wr(dcu_ram_data1_wr),
    .dcu_ram_data1_addr(dcu_ram_data1_addr),
    .dcu_ram_data1_wen(dcu_ram_data1_wen),
    .dcu_ram_data1_wdata(dcu_ram_data1_wdata),
    .dcu_ram_data1_rdata(dcu_ram_data1_rdata),
    
    // RAS接口
    .dcu_ras_valid(),
    .dcu_ras_ce(),
    .dcu_ras_ued(),
    .dcu_ras_uec(),
    .dcu_ras_priority(),
    .dcu_ras_tt(),
    .dcu_ras_scrub(),
    .dcu_ras_ec(),
    .dcu_ras_addr(),
    .dcu_ras_aec(),
    .dcu_ras_tag(),
    .dcu_ras_way(),
    
    // PMU接口
    .dcu_pmu_access(),
    .dcu_pmu_miss(),
    
    // 时钟和复位
    .clk(clk),
    .rst_n(rst_n)
);

// 时钟生成
initial begin
    clk = 0;
    forever #5 clk = ~clk;
end

task r_return0();
    #0 bmu_dcu_r_vld = 1'b1; 
    #0 bmu_dcu_r_id  = 12'h1;
    #0 bmu_dcu_r_data = 64'h88;
    #0 bmu_dcu_r_resp = 2'b00;
    #0 bmu_dcu_r_last = 1'b1;
    @(posedge clk); 
    #0 bmu_dcu_r_vld = 1'b0; 
    #0 bmu_dcu_r_id  = 12'h0;
    #0 bmu_dcu_r_data = 64'h00;
    #0 bmu_dcu_r_resp = 2'b00;
    #0 bmu_dcu_r_last = 1'b0;
endtask

task r_return1();
    #0 bmu_dcu_r_vld = 1'b1; 
    #0 bmu_dcu_r_id  = 12'h1;
    #0 bmu_dcu_r_data = {32'h11,32'h22};
    #0 bmu_dcu_r_resp = 2'b00;
    #0 bmu_dcu_r_last = 1'b0;
    @(posedge clk); 
    #0 bmu_dcu_r_vld = 1'b1; 
    #0 bmu_dcu_r_id  = 12'h1;
    #0 bmu_dcu_r_data = {32'h33,32'h44};
    #0 bmu_dcu_r_resp = 2'b00;
    #0 bmu_dcu_r_last = 1'b0;
    @(posedge clk); 
    #0 bmu_dcu_r_vld = 1'b1; 
    #0 bmu_dcu_r_id  = 12'h1;
    #0 bmu_dcu_r_data = {32'h55,32'h66};
    #0 bmu_dcu_r_resp = 2'b00;
    #0 bmu_dcu_r_last = 1'b0;
    @(posedge clk); 
    #0 bmu_dcu_r_vld = 1'b1; 
    #0 bmu_dcu_r_id  = 12'h1;
    #0 bmu_dcu_r_data = {32'h77,32'h88};
    #0 bmu_dcu_r_resp = 2'b00;
    #0 bmu_dcu_r_last = 1'b1;
    @(posedge clk); 
    #0 bmu_dcu_r_vld = 1'b0; 
    #0 bmu_dcu_r_id  = 12'h0;
    #0 bmu_dcu_r_data = {32'h00,32'h00};
    #0 bmu_dcu_r_resp = 2'b00;
    #0 bmu_dcu_r_last = 1'b0;
endtask

task r_return_sbu();
    #0 bmu_dcu_r_vld = 1'b1; 
    #0 bmu_dcu_r_id  = 12'h1;
    #0 bmu_dcu_r_data = {32'h8800,32'h7700};
    #0 bmu_dcu_r_resp = 2'b00;
    #0 bmu_dcu_r_last = 1'b0;
    @(posedge clk); 
    #0 bmu_dcu_r_vld = 1'b1; 
    #0 bmu_dcu_r_id  = 12'h1;
    #0 bmu_dcu_r_data = {32'h6600,32'h5500};
    #0 bmu_dcu_r_resp = 2'b00;
    #0 bmu_dcu_r_last = 1'b0;
    @(posedge clk); 
    #0 bmu_dcu_r_vld = 1'b1; 
    #0 bmu_dcu_r_id  = 12'h1;
    #0 bmu_dcu_r_data = {32'h4400,32'h3300};
    #0 bmu_dcu_r_resp = 2'b00;
    #0 bmu_dcu_r_last = 1'b0;
    @(posedge clk); 
    #0 bmu_dcu_r_vld = 1'b1; 
    #0 bmu_dcu_r_id  = 12'h1;
    #0 bmu_dcu_r_data = {32'h2200,32'h1100};
    #0 bmu_dcu_r_resp = 2'b00;
    #0 bmu_dcu_r_last = 1'b1;
    @(posedge clk); 
    #0 bmu_dcu_r_vld = 1'b0; 
    #0 bmu_dcu_r_id  = 12'h0;
    #0 bmu_dcu_r_data = {32'h0000,32'h0000};
    #0 bmu_dcu_r_resp = 2'b00;
    #0 bmu_dcu_r_last = 1'b0;
endtask


//all signal initial
initial begin
    #0 bmu_dcu_r_vld = 1'b0; 
    #0 bmu_dcu_r_id  = 12'h0;
    #0 bmu_dcu_r_data = 64'h0;
    #0 bmu_dcu_r_resp = 2'b00;
    #0 bmu_dcu_r_last = 1'b0;

    //init SBU
    #0 sbu_dcu_tag_req_vld_m1   = 1'b0; 
    #0 sbu_dcu_tag_req_addr_m1  = 32'h0;
    #0 sbu_dcu_tag_req_sbqid_m1 = 3'h0;
    #0 sbu_dcu_tag_req_excl_m1  = 1'b00; //no excl
    #0 sbu_dcu_tag_req_idempotency_m1 = 1'b0; //non-device
    #0 sbu_dcu_tag_req_inner_ma_m1 = 3'b111;
    #0 sbu_dcu_tag_req_outer_ma_m1 = 3'b111;
    #0 sbu_dcu_tag_req_priv_m1 = 1'b0;
    #0 sbu_dcu_tag_req_master_m1 = 1'b0;
    #0 sbu_dcu_tag_req_cmoop_m1 = 'b0;

end

// 测试激励
initial begin
    // 初始化
    rst_n = 0;
    #20;
    rst_n = 1;
    repeat (1024) @(posedge clk);

    //1. load req miss  
    //addr=08
    @(posedge clk);
    lsu_dcu_ld_req_valid_m1    = 2'b01;
    lsu_dcu_ld_req_addr_m1[0]  = 32'h08;
    lsu_dcu_ld_req_size_m1[0]  = 2'b11;
    lsu_dcu_ld_req_lsqid_m1    = 12'h1;
    
    @(posedge clk);
    lsu_dcu_ld_req_valid_m1    = 2'b00;
    lsu_dcu_ld_req_addr_m1[0]  = 32'h00;
    lsu_dcu_ld_req_size_m1[0]  = 2'b00;
    lsu_dcu_ld_req_lsqid_m1    = 12'h0;

    repeat (10) @(posedge clk);
    r_return1();

    //2. load req hit
    //addr=18
    @(posedge clk);
    lsu_dcu_ld_req_valid_m1    = 2'b01;
    lsu_dcu_ld_req_addr_m1[0]  = 32'h18;
    lsu_dcu_ld_req_size_m1[0]  = 2'b11;
    lsu_dcu_ld_req_lsqid_m1    = 12'h2;
    
    @(posedge clk);
    lsu_dcu_ld_req_valid_m1    = 2'b00;
    lsu_dcu_ld_req_addr_m1[0]  = 32'h00;
    lsu_dcu_ld_req_size_m1[0]  = 2'b00;
    lsu_dcu_ld_req_lsqid_m1    = 12'h0;
    
    //3. store req hit
    #0 sbu_dcu_tag_req_vld_m1   = 1'b1; 
    #0 sbu_dcu_tag_req_addr_m1  = 32'h24;
    #0 sbu_dcu_tag_req_sbqid_m1 = 3'h5;
    #0 sbu_dcu_tag_req_excl_m1  = 1'b00; //no excl
    #0 sbu_dcu_tag_req_idempotency_m1 = 1'b1; //non-device
    #0 sbu_dcu_tag_req_inner_ma_m1 = 3'b111;
    #0 sbu_dcu_tag_req_outer_ma_m1 = 3'b111;
    #0 sbu_dcu_tag_req_priv_m1 = 1'b0;
    #0 sbu_dcu_tag_req_master_m1 = 1'b0;
    @(posedge clk);
    #0 sbu_dcu_tag_req_vld_m1   = 1'b0; 
    #0 sbu_dcu_tag_req_addr_m1  = 32'h0;
    #0 sbu_dcu_tag_req_sbqid_m1 = 3'h0;
    #0 sbu_dcu_tag_req_excl_m1  = 1'b00; //no excl
    #0 sbu_dcu_tag_req_idempotency_m1 = 1'b0; //non-device
    #0 sbu_dcu_tag_req_inner_ma_m1 = 3'b000;
    #0 sbu_dcu_tag_req_outer_ma_m1 = 3'b000;
    #0 sbu_dcu_tag_req_priv_m1 = 1'b0;
    #0 sbu_dcu_tag_req_master_m1 = 1'b0;

    repeat (10) @(posedge clk);
    r_return_sbu();


    //4. dirty wrback



    
    #100;
end


initial begin
#250000 $finish();   //vcs simulate time finish
end

initial begin
    $fsdbDumpfile("novas.fsdb");
    $fsdbDumpvars();
    $fsdbDumpMDA();
end

endmodule 